circuit-analysis-dc-ac

# Circuit Analysis: DC and AC

Circuit analysis is the engineering discipline of predicting the behavior of a network of resistors, capacitors, inductors, voltage and current sources, and dependent sources using a small catalog of laws and transformations. Everything downstream — amplifier design, filter design, power supply design, feedback stability, oscillator start-up — ultimately reduces to getting the underlying DC bias and AC small-signal analysis right. This skill catalogs the core techniques in the order they are typically applied and shows how to move fluently between the time domain, the phasor (frequency) domain, and the Laplace domain.

**Agent affinity:** shockley (device bias and load lines), horowitz (intuition building and worked examples)

**Concept IDs:** elec-ohms-law-fundamentals, elec-passive-component-behavior, elec-signal-ac-analysis

## The Core Laws

Every linear circuit obeys three laws. Everything else in this skill is a consequence of how these three are applied.

| # | Law | Statement | Use for |
|---|---|---|---|
| 1 | Ohm's law | V = IR for resistors; V = IZ for general impedances | Relating voltage and current across a single element |
| 2 | Kirchhoff's voltage law (KVL) | The sum of voltage drops around any closed loop is zero | Writing one equation per mesh |
| 3 | Kirchhoff's current law (KCL) | The sum of currents entering any node equals the sum leaving | Writing one equation per node |

KVL is conservation of energy around a loop. KCL is conservation of charge at a node. Ohm's law is the constitutive relation. A correct analysis uses exactly as many independent equations as there are unknown node voltages or mesh currents.

## Technique 1 — Series and Parallel Reduction

**Pattern:** Collapse runs of resistors (or impedances) using R_series = R_1 + R_2 + ... and 1/R_parallel = 1/R_1 + 1/R_2 + ... until the circuit is reduced to a single element seen by the source.

**Worked example.** A 10 kΩ resistor in series with the parallel combination of 20 kΩ and 30 kΩ.

The parallel combination is (20 * 30) / (20 + 30) = 600 / 50 = 12 kΩ. The total is 10 kΩ + 12 kΩ = 22 kΩ. If the source is 11 V, the total current is 0.5 mA, the drop across the 10 kΩ resistor is 5 V, and the remaining 6 V appears across the parallel pair.

**When to use.** First pass on every problem. If the circuit reduces cleanly, you may not need any further technique. Reduction fails as soon as a branch contains a non-grounded source or a dependent source whose controlling variable lives inside the region being collapsed.

## Technique 2 — Voltage and Current Dividers

**Voltage divider.** Two resistors R_1 and R_2 in series across a source V_s produce V_out = V_s * R_2 / (R_1 + R_2) across R_2. Loaded dividers require including the load resistance in parallel with R_2.

**Current divider.** Two parallel resistors split a total current I_total such that the current through R_1 is I_total * R_2 / (R_1 + R_2). The lower-resistance branch gets more current.

**Practical rule.** A voltage divider driving a load needs its Thevenin source resistance small compared to the load (typically at least 10x smaller) for the divider ratio to hold within a few percent. Ignoring this rule is the most common first-year error.

## Technique 3 — Nodal Analysis

**Pattern:** Pick a reference node (ground). Label every other node with a voltage variable. Write KCL at each labeled node in terms of node voltages and the conductances connecting them. Solve the resulting linear system.

**Worked example.** Three nodes labeled A, B, and ground. A 10 V source drives node A through a 1 kΩ resistor; a 2 kΩ resistor connects A to B; a 3 kΩ resistor connects B to ground. KCL at A: (10 - V_A)/1k = (V_A - V_B)/2k. KCL at B: (V_A - V_B)/2k = V_B/3k. Solving the 2x2 system yields V_A ≈ 6.92 V and V_B ≈ 4.15 V.

**When to use.** Circuits with many nodes and few loops; circuits where node voltages are the natural output (e.g., amplifier outputs). Nodal analysis is also the basis of modified nodal analysis, the core algorithm in SPICE.

## Technique 4 — Mesh Analysis

**Pattern:** Identify independent loops (meshes). Assign a clockwise mesh current to each. Write KVL around each mesh in terms of mesh currents and the impedances in each branch. Solve the linear system.

**Worked example.** A two-mesh circuit with mesh currents I_1 and I_2 sharing a 4 kΩ resistor. Mesh 1 has a 12 V source, a 2 kΩ resistor, and the shared 4 kΩ resistor. Mesh 2 has the shared 4 kΩ and a 6 kΩ to ground. KVL mesh 1: 12 = 2k * I_1 + 4k * (I_1 - I_2). KVL mesh 2: 0 = 4k * (I_2 - I_1) + 6k * I_2. Solving yields I_1 ≈ 2.4 mA and I_2 ≈ 0.96 mA.

**When to use.** Circuits with few loops and many nodes; circuits where branch currents are the natural output. For planar circuits the number of mesh equations equals the number of independent loops.

## Technique 5 — Superposition

**Pattern:** For a linear circuit with multiple independent sources, compute the response due to each source alone (with all other independent sources set to zero — voltage sources shorted, current sources opened), then sum the individual responses.

**Worked example.** A circuit with a 5 V source and a 2 mA current source. Compute the voltage across a target resistor with only the 5 V source present, then again with only the current source present, then add. The total is the true steady-state voltage.

**Restrictions.** Superposition applies only to linear elements. It does not apply to power (power is quadratic), and it does not apply when the circuit contains nonlinear elements in the region of operation being analyzed.

## Technique 6 — Thevenin and Norton Equivalents

**Thevenin.** Any linear two-terminal network is equivalent, from the terminals' perspective, to a single voltage source V_th in series with a resistance R_th. V_th is the open-circuit voltage; R_th is the ratio V_open / I_short (or the resistance seen looking in with independent sources zeroed).

**Norton.** The